(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically for fabricating self-aligned metal barriers by atomic layer deposition, ALD, capable of producing extremely thin, uniform, and conformal metal barrier films, selectively depositing on copper, not on silicon dioxide interlevel dielectric, in multi-layer dual damascene trench/via processing.
(2) Description of Related Art
In this section a description of related Prior Art background patents follows.
U.S. Pat. No. 6,274,932 B1 entitled “Semiconductor Device Having Metal Interconnection Comprising Metal Silicide And Four Conductive Layer” granted Aug. 14, 2001 to Mikagi describes a tantalum barrier layer for a copper dual damascene interconnect. A semiconductor device has a metal interconnection that includes an insulating film provided on a semiconductor substrate. An interlayer contact hole is formed in the insulating film. A metal silicide layer is provided at the bottom of the interlayer contact hole. A first conductive film comprises a single or a plurality of metal films provided on the insulating film and the interlayer contact hole. A second conductive film is provided in the interlayer contact hole. A third conductive film is provided on the first conductive film and the second conductive film. A fourth conductive film is provided on the third conductive film. This semiconductor device has improved durability with respect to electromigration.
U.S. Pat. No. 6,287,965 B1 entitled “Method Of Forming Metal Layer Using Atomic Layer Deposition And Semiconductor Device Having The Metal Layer As Barrier Metal Layer Or Upper Or Lower Electrode OF Capacitor” granted Sep. 11, 2001 to Kang et al. describes a Ta or Nb atomic layer deposited layer as a metal barrier layer. A method of forming a metal layer having excellent thermal and oxidation resistant characteristics using atomic layer deposition is provided. The metal layer includes a reactive metal (A), an element (B) for the amorphous combination between the reactive metal (A) and nitrogen (N), and nitrogen (N). The reactive metal (A) may be titanium (Ti), tantalum (Ta), tungsten (W), zirconium (Zr), hafnium (Hf), molybdenum (Mo) or niobium (Nb). The amorphous combination element (B) may be aluminum (Al), silicon (Si) or boron (B). The metal layer is formed by alternately injecting pulsed source gases for the elements (A, B and N) into a chamber according to atomic layer deposition to thereby alternately stack atomic layers. Accordingly, the composition ratio of a nitrogen compound (A-B—N) of the metal layer can be desirably adjusted just by appropriately determining the number of injection pulses of each source gas. According to the composition ratio, a desirable electrical conductivity and resistance of the metal layer can be accurately obtained. The atomic layers are individually deposited, thereby realizing excellent step coverage even in a complex and compact region. A metal layer formed by atomic layer deposition can be employed as a barrier metal layer, a lower electrode or an upper electrode in a semiconductor device.
U.S. Pat. No. 6,284,646 B1 entitled “Methods Of Forming Smooth Conductive Layers For Integrated Circuit Devices” granted Sep. 4, 2001 to Leem describes a Ta barrier layer deposited by atomic layer deposition. The method for forming a metal layer for an integrated circuit device includes forming a first conductive layer on an integrated circuit substrate. While forming the first conductive layer, a reflection index of the first conductive layer is monitored, and the formation of the first conductive layer is terminated when the reflection index of the first conductive layer reaches a predetermined value. More particularly, the first conductive layer can be an aluminum layer having a thickness in the range of approximately 500 Angstroms to 1500 Angstroms.
U.S. Pat. No. 6,291,334 B1 entitled “Etch Stop Layer For Dual Damascene Process” granted Sep. 18, 2001 to Somekh et al. describes a Ta barrier layer in a dual damascene process. The method provides a carbon based etch stop, such as a diamond like amorphous carbon, having a low dielectric constant and teaches a method of forming a dual damascene structure. The low k etch stop is preferably deposited between two dielectric layers and patterned to define the underlying interlevel contacts/vias. The second or upper dielectric layer is formed over the etch stop and patterned to define the intralevel interconnects. The entire dual damascene structure is then etched in a single selective etch process which first etches the patterned interconnects, then etches the contact/vias past the patterned etch stop. The etch stop has a low dielectric constant relative to a conventional SiN etch stop, which minimizes the capacitive coupling between adjacent interconnect lines. The dual damascene structure is then filled with a suitable conductive material such as aluminum or copper and planarized using chemical mechanical polishing.
U.S. Pat. No. 6,281,127 B1 entitled “Self-Passivation Procedure For A Copper Damascene Structure” granted Aug. 28, 2001 to Shue shows a barrier cap over a copper dual damascene interconnect. Processes for creating a boron containing copper region, in a top portion of a copper damascene structure, are disclosed. The boron containing copper region, used to protect exposed regions of the copper damascene structure, from reactants used for subsequent processing procedures, can be formed via ion implantation of boron ions, placed in exposed regions of the copper damascene structure, after completion of an initial CMP procedure. The copper damascene structure is then protected by the boron containing copper region, during subsequent processing procedures, such as a final CMP procedure, employed to insure complete removal of unwanted materials, as well as during subsequent CVD procedures, using NH3 and SiH4, as reactants.
U.S. Pat. No. 6,258,713 B1 entitled “Method For Forming Dual Damascene Structure” granted Jul. 10, 2001 to Yu et al. shows a cap barrier layer over a copper dual damascene interconnect. A first dielectric layer is formed over a substrate, and then the first dielectric layer is planarized. The first dielectric layer is etched to form a dual damascene opening that includes a via opening and a trench. The via opening exposes a conductive layer in the substrate. A metallic is formed in the via openings and the trenches so that a metallic interconnect and a via are formed at the same time. A cap layer is formed on the metallic layer. An additional etching stop layer may form on the cap layer and the substrate. A second dielectric layer is formed over the substrate. The second dielectric layer is etched to form a via opening that exposes a portion of the cap layer.